The following information represents dTSEC5 and FMan status after the reception of several packets. FMBM_PFS_12 (FIFO parameters for dTSEC5 RX) = 0x0000000F FMBM_PP_12 (port parameters for dTSEC5 RX) = 0x03000000 Here are the parameters of my dTSEC5/FMan configuration: Any help on this matter would be appreciated. When compared to the dTSEC5/FMan configuration performed by UBoot, where proper dTSEC5 RX port operation was observed (packet data was transferred to DDR RAM with the RxQD and RX BD fields updated correctly), I believe my driver software is correct however, I have to be missing something. At this point, it appears that the MAC is receiving packets because I see the packets’ data stored in the FMan buffer pool memory, but the data is not transferred to DDR RAM, the Offset In field in the RxQD is not advanced to the next RX buffer descriptor, and the Empty bit is not cleared in the current RX buffer descriptor. After dTSEC5, FMan, and the PHY device are initialized, auto-negotiation successfully completes and a link is present as reported by the PHY device. In this software, I am configuring dTSEC5 for Ethernet Independent mode receive and transmit processing. I am developing bare-metal Ethernet driver software on an XPedite5470 board with the P5020 processor.
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